In recent years, techniques for reducing parasitic capacitance have been under development in order to improve the performance of semiconductor devices. The techniques for reducing parasitic capacitance include a silicon-on-sapphire (SOS) structure.
There is a method for producing the SOS structure by bonding substrates composed of different materials together. An example of the method for bonding substrates composed of different materials is a normal-temperature bonding method. The basic technical content of the normal-temperature bonding method is described in, for example, Japanese Patent No. 2791429. In Japanese Patent No. 2791429, surfaces of two substrates are activated and brought into contact with each other to bond the substrates composed of different materials.